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features avago 1310nm distributed feedback (dfb) source and transmitter optical subassembly technology avago pin detector and receiver optical subassembly technology typical power dissipation 850mw full digital diagnostic management interface avago sfp+ package design enables equipment emi performance in high port density applications with margin to class b limits flexibility in data rate selection through either hardware or software control specifications optical interface specifications per ieee 802.3ae 10gbase-lr compliant to the transmitter extinction ratio and the receiver sensitivity specs per ieee 802.3 gigabit ethernet (1.25gbd) 1000base-lx electrical interface specifications per sff committee sff 8431 specifications for enhanced 8.5 and 10 gigabit small form factor pluggable module sfp+ management interface specifications per sff com- mittee sff 8431 and sff 8472 diagnostic monitoring interface for optical transceivers mechanical specifications per sff committee sff 8432 improved pluggable formfactor ipf lc duplex optical connector interface confirming to ansi tia/ea 604-10 (focis 10a) compliant to restriction on hazardous substances (rohs) per eu and china requirements compliant to halogen free requirement class 1 eye safe per requirements of iec 60825-1/ cdrh description the avago afct-701sddz transceiver is part of a fam- ily of sfp+ products. this transceiver utilizes avagos 1310nm dfb and pin detector technology to provide an ieee 10gb ethernet design compliant with the 10gbase- lr standard and allows for the operation at 1.25gbd for gigabit ethernet applications. the afct-701sddz trans- ceiver has the signal and the chassis sfp grounds tied together to enhance the emi shielding performance of the module, providing extra margin that is particularly useful in higher density applications. the design is based on the new electrical and mechanical specification en- hancements to the well known sfp specifications de- veloped by the sff committee. these specifications are referred to as sfp+ to recognize these enhancements to previous sfp specifications used for lower speed prod- ucts. avago technologies is an active participant in the sff committee specification development activities. related products afbr-703sddz sfp+ 10gb/1gb gigabit ethernet 10gbase-sr transceiver for operation in om3 mmf link applications with link length up to 300 meters afct-701sdz(afct-701asdz) sfp+ 10 gigabit ethernet 10gbase-lr transceiver with case temperature 0-70 c (0-85 c) for operation in smf link applications with link lengths up to 10 km. afbr-707sdz sfp+ 10 gigabit ethernet 10gbase- lrm transceiver for 220 meter operation in all mmf link applications including om1 and om2 legacy fiber cables and new high bandwidth om3 fiber cables. afct-5016z sfp+ evaluation board the purpose of this sfp+ evaluation board is to provide the designer with a convenient means for evaluating sfp+ fiber optic transceivers. afct-701sddz 10gb/1gb ethernet, 1310nm sfp+ transceiver data sheet afct-701sddz
2 installation the afct-701sddz transceiver package is compliant with the sff 8432 improved pluggable formfactor hous- ing specification for the sfp+. it can be installed in any inf-8074 or sff-8431/2 compliant small form pluggable (sfp) port regardless of host equipment operating status the afct-701sddz is hot-pluggable, allowing the mod- ule to be installed while the host system is operating and on-line. upon insertion, the transceiver housing makes initial contact with the host board sfp cage, mitigating potential damage due to electro-static discharge (esd). by selecting tx rate select to 1.25 gbps operation, the tx module performance complies with the extinction ratio and output power level in the 1000base-lx specifica- tions. likewise rx performance complies with the sensitivity performance in the 1000base-lx by selecting rx rate select to 1.25 gbps operation. the rate select can be done through either the hardware pins or the software access to the a2h page of eeprom map. the user can refer to the appendix for details of rate select. digital diagnostic interface and serial identification the two-wire interface protocol and signaling detail are based on sff-8431. conventional eeprom memory, bytes 0-255 at memory address 0xa0, is organized in compliance with sff-8431. new digital diagnostic in- formation, bytes 0-255 at memory address 0xa2, is compliant to sff-8472. the new diagnostic information provides the opportunity for predictive failure identifi- cation, compliance prediction, fault isolation and com- ponent monitoring. predictive failure identification the afct-701sddz predictive failure feature allows a host to identify potential link problems before system performance is impacted. prior identification of link problems enables a host to service an application via fail over to a redundant link or replace a suspect de- vice, maintaining system uptime in the process. for ap- plications where ultra-high system uptime is required, a digital sfp provides a means to monitor two real-time laser metrics asso ciated with laser degradation and pre- dicting failure: average laser bias current (tx_bias) and average laser optical power (tx_power). compliance prediction compliance prediction is the ability to determine if an optical transceiver is opera ting within its operating and environmental requirements. afct-701sddz devices provide real-time access to transceiver internal supply voltage and temperature, allowing a host to identify potential component compliance issues. received optical power is also available to assess compliance of a cable plant and remote tr ansmitter. when operating out of requirements, the link cannot guarantee error free transmission. fault isolation the fault isolation feature allows a host to quickly pin- point the location of a link failure, minimizing down- time. for optical links, the ability to identify a fault at a local device, remote device or cable plant is crucial to speeding service of an installation. afct-701sddz real- time monitors of tx_bias, tx_power, vcc, temperature and rx_power can be used to assess local transceiver current operating conditions. in addition, status flags tx_disable and rx loss of signal (los) are mirrored in memory and available via the two-wire serial interface. component monitoring component evaluation is a more casual use of the afct- 701sddz real-time monitors of tx_bias, tx_power, vcc, temperature and rx_power. potential uses are as de- bugging aids for system installation and design, and transceiver parametric evaluation for factory or field qualification. for example, temperature per module can be observed in high density applications to facilitate thermal evaluation of blades, pci cards and systems. description, continued
3 figure 1. transceiver functional diagram transmit fault (tx_fault) a catastrophic laser fault will activate the transmitter signal, tx_fault, and disable the laser. this signal is an open collector output (pull-up required on the host board). a low signal indicates normal laser operation and a high signal indicates a fault. a fault is defined as laser power below or above the specified ieee 802.3ae speci- fied min/max range. the tx_fault will be latched high when a laser fault occurs and is cleared by toggling the tx_disable input or power cycling the transceiver. the transmitter fault condition can also be monitored via the two-wire serial interface (address a2, byte 110, bit 2). transmitter section the transmitter section includes the transmitter optical sub-assembly (tosa) and laser driver circuitry. the tosa, containing an avago designed and manufactured 1310 nm dfb light source, is located at the optical inter- face and mates with the lc optical connector. the tosa is driven by an ic which uses the incoming differential high speed logic signal to modulate the laser diode driver current. this tx laser driver circuit regulates the optical power at a level within the specified range. transmit disable (tx_disable) the afct-701sddz accepts an lvttl compatible trans- mit disable control signal input which shuts down the transmitter optical output. a high signal implements this function while a low signal allows normal transceiver operation. in the event of a fault (e.g. eye safety circuit activated), cycling this control signal resets the module as depicted in figure 5. an internal pull up resistor dis- ables the transceiver transmitter until the host pulls the input low. tx_disable can also be asserted via the two- wire interface (address a2h, byte 110, bit 6) and moni- tored (address a2h, byte 110, bit 7). the contents of a2h, byte 110, bit 6 are logic ord with hardware tx_disable (contact 3) to control transmitter operation. the normal behavior of this feature is to reset a tx disabled transceiver to tx enabled when it is power cycled or hot-plugged. l ight f r o m fi ber l ight to fi ber p hoto- de t ec to r rece iv er ampl ifi ca tion & q ua nti za tion rd + (rece iv e da t a) rd C (rece iv e da t a) rx _ l o s v csel t ra n sm itt er laser dr iv er & sa f e ty c i rcu it r y t x _ d i sable t d + ( t ra n sm it da t a) t d C ( t ra n sm it da t a) t x _f aul t elec t r i cal int er f ace sda scl m o d - abs c ont r o ller & mem o r y o p ti cal int er f ace rs0 rs 1
4 receiver section the receiver section includes the receiver optical sub- assembly (rosa) and the amplification/quantization circuitry. the rosa, containing a pin photodiode and custom transimpedance amplifier, is located at the op- tical interface and mates with the lc optical connector. the rosa output is fed to a custom ic that provides post-amplification and quantization. receiver loss of signal (rx_l o s) the post-amp ic also includes transition detection cir- cuitry which monitors the ac level of incoming optical signals and provides a lvttl/cmos compatible status signal to the host. a high status signal indicates loss of modulated signal, indicating link failures such as broken fiber or failed transmitter. rx_los can also be monitored via the two-wire serial interface (address a2h, byte 110, bit 1). functional data i/ o the afct-701sddz interfaces with the host circuit board through the twenty contact sfp+ electrical connector. see table 2 for contact descriptions. the module edge connector is shown in figure 3. the afct-701sddz high speed transmit and receive in- terfaces require sff-8431 compliant signal lines on the host board. to simplify board requirements, biasing re- sistors and ac coupling capacitors are incorpo rated into the sfp+ transceiver module (per sff-8431) and hence are not required on the host board. the tx_disable, tx_fault and rx_los signals require lvttl signals on the host board (per sff-8431) if used. if an application does not take advantage of these func tions, care must be taken to ground tx_disable to enable normal op- eration. figure 2 depicts the recom mended interface circuit to link the afct-701sddz to supporting physical layer ics. timing for the dedicated sfp+ control signals imple- mented in the transceiver is shown in figure 5. application support an evaluation kit and reference designs are available to assist in evaluation of the afct-701sddz. please contact your local field sales representative for availability and ordering details. caution there are no user serviceable parts nor maintenance requirements for the afct-701sddz. all mechanical adjustments are made at the factory prior to shipment. tampering with, modifying, misusing or improperly han- dling the afct-701sddz will void the product warranty. it may also result in improper operation and possibly overstress the laser source. performance degrada tion or device failure may result. connection of the afct-701 sddz to a light source not compliant with ieee std. 802.3ae clause 52 and sff-8341 specifications, operat- ing above maximum operating conditions or in a man- ner inconsistent with its design and function may result in exposure to hazardous light radiation and may consti- tute an act of modifying or manufacturing a laser prod- uct. persons performing such an act are required by law to recertify and re-identify the laser product under the provisions of u.s. 21 cfr (subchapter j) and tuv. customer manufacturing processes this module is pluggable and is not designed for aque- ous wash, ir reflow, or wave soldering processes. o rdering information please contact your local field sales engineer or one of avago technologies franchised distributors for order- ing information. for technical information, please visit avago technologies web page at www.avagotech.com. for information related to sff committee documenta- tion visit www.sffcommittee.org.
5 electromagnetic interference (emi) equipment incorporating 10 gigabit transceivers is typically subject to regulation by the fcc in the united states, cenelec en55022 (cispr 22) in europe and vcci in japan. the afct-701sddz enables equipment com- pliance to these standards detailed in table 1. the metal housing and shielded design of the afct-701sddz min- imizes the emi challenge facing the equipment designer. for superior emi performance it is recommended that equipment designs utilize sfp+ cages per sff 8432. rf immunity (susceptibility) due to its shielded design, the emi immunity of the afct-701sddz exceeds typical industry standards. eye safety the afct-701sddz provides class 1 (single fault tolerant) eye safety by design and has been tested for compliance with the requirements listed in table 1. the eye safety circuit continuously monitors the optical output power level and will disable the transmitter upon detecting a condition beyond the scope of class 1 certi- fication such conditions can be due to inputs from the host board (vcc fluctuation, unbalanced code) or a fault within the transceiver. us cdrh and eu tuv certificates are listed in table 1. flammability the afct-701sddz optical transceiver is made of metal and high strength, heat resistant, chemical resistant and ul 94v-0 flame retardant plastic. regulatory compliance the afct-701sddz complies with all applicable laws and regulations as detailed in table 1. certification level is dependent on the overall configuration of the host equipment. the transceiver performance is offered as a figure of merit to assist the designer. electrostatic discharge (esd) the afct-701sddz is compatible with esd levels found in typical manufacturing and operating environments as described in table 1. in the normal handling and operation of optical transceivers, esd is of concern in two circumstances. the first case is during handling of the transceiver pri- or to insertion into an sfp compliant cage. to protect the device, its important to use normal esd handling pre-cautions. these include use of grounded wrist straps, work-benches and floor wherever a transceiver is handled. the second case to consider is static discharges to the exterior of the host equipment chassis after installation. if the optical interface is exposed to the exterior of host equipment cabinet, the transceiver may be subject to system level esd requirements.
6 table 1. regulatory compliance feature test method performance electrostatic discharge (esd) mil-std883c method 3015.4 class 1 (> 1kv) for high speed i/o pins to the electrical contacts jedec desd22-a11-4-b class 1 (> 2kv) for all other pins electrostatic discharge (esd) iec 61000-4-2 typically, no damage occurs with 25 kv when to the duplex lc receptacle the duplex lc connector receptacle is contacted by a human body model probe. life traffic esd immunity iec 61000-4-2 10 contacts of 8 kv on the electrical faceplate with device inserted into a panel. life traffic esd immunity iec 61000-4-2 air discharge of 15 kv (min.) contact to connector without damage. electromagnetic fcc class b system margins are dependent on customer interference (emi) cenelec en55022 class b board and chassis design. (cispr 22a) vcci class 1 rf immunity iec 61000-4-3 typically shows no measurable effect from a 10 v/m field swept from 80mhz to 1 ghz laser eye safety and us fda cdrh ael class 1 cdrh accession no. 9521220-158 equipment type testing us21 cfr, subchapter j per pending completion paragraphs 1002.10 and 1002.12 (iec) en60825-1: 1994 + a11 + a2 (iec) en60825-2: 1994 + a1 (iec) en60950: 1992 + a1 + a2 + a3 + a4 + a11 component recognition underwriters laboratories and canadian ul file e173874 standards association joint component recognition for information technology equipment including electrical business equipment rohs compliance rohs directive 2002/95/ec and sgs test report no. lpc1/00895/08 its amendment directives 6/6 cts ref. cts/08-0238/avago bauar t g epru ft ty pe appr ov ed t u v rhein l and produc t safe t y
7 figure 2. typical application configuration laser dr iv er m o dule de t ec t l o ss of s ign al scl sda t x _f aul t t x _ d i sable t d + t x _f aul t t x _ d i sable t d C rd + rd C sda scl m o d _ abs v eer 4 .7 k t o 1 0 k 5 0 5 0 1 . 1 k t o 8 k 1 . 1 k t o 8 k 4 .7 k t o 1 0 k pr oto c o l i c v cc t rs0 v cc htwi serdes i c rx _ l o s v ee t 0. 1 f 0. 1 f p o s t ampl ifi er v cc h os t 1 00 rs 1 4 .7 k t o 1 0 k 1 00 1 0 k 0. 1 f v ccr 0. 1 f v ccr 0. 1 f 22 f 0. 1 f 4 .7u h dcr = 0. 15 v cc h os t 0. 1 f 22 f 0. 1 f 4 .7u h dcr = 0. 15 v cc t v ccr . . 0. 5 0. 5
8 n otes: 1. the module signal grounds are isolated from the module case. 2. this is an open collector/drain output that on the host board requires a 4.7 k to 10 k pullup resistor to vcchost. see figure 2. 3. this input is internally biased high with a 4.7 k to 10 k pullup resistor to vcct. 4. two-wire serial interface clock and data lines require an external pullup resistor dependent on the capacitance load. 5. this is a ground return that on the host board requires a 4.7 k to 10 k pullup resistor to vcchost. 6. refer to the appendix for detailed operation of rs0 and rs1. table 2. contact description contact symbol function/description n otes 1 veet transmitter signal ground note 1 2 tx_fault transmitter fault (lvttl-o) C high indicates a fault condition note 2 3 tx_disable transmitter disable (lvttl-i) C high or open disables the transmitter note 3 4 sda two wire serial interface data line (lvcmos C i/o) (same as mod-def2 in inf-8074) note 4 5 scl two wire serial interface clock line (lvcmos C i/o) (same as mod-def1 in inf-8074) note 4 6 mod_abs module absent (output), connected to veet or veer in the module note 5 7 rs0 rate select 0 - rs0=lo for 1000base-lx, rs0=hi for 10gbase-lr note 6 8 rx_los receiver loss of signal (lvttl-o) note 2 9 rs1 rate select 1 - rs1=lo for 1000base-lx, rs1=hi for 10gbase-lr note 6 10 veer receiver signal ground note 1 11 veer receiver signal ground note 1 12 rd- receiver data out inverted (cml-o) 13 rd+ receiver data out (cml-o) 14 veer receiver signal ground 15 vccr receiver power + 3.3 v 16 vcct transmitter power + 3.3 v 17 veet transmitter signal ground note 1 18 td+ transmitter data in (cml-i) 19 td- transmitter data in inverted (cml-i) 20 veet transmitter signal ground note 1 figure 3. module edge connector contacts to p vi e w of b o ard 11 20 1 0 1 tow ard ho s t b otto m of b o ard as vi e w ed f r o m to p th r o u gh b o ard
9 table 3. absolute maximum ratings stress in excess of any of the individual absolute maximum ratings can cause immediate catastrophic damage to the module even if all other parameters are within recommended operating conditions. it should not be assumed that limiting values of more than one parameter can be applied concurrently. exposure to any of the absolute maximum ratings for extended periods can adversely affect reliability. parameter symbol minimum maximum unit n otes storage temperature t s -40 100 c case operating temperature t c -40 100 c relative humidity rh 5 95 % supply voltage vcct, vccr -0.3 3.8 v note 1 low speed input voltage -0.5 vcc+0.5 v two-wire interface input voltage -0.5 vcc+0.5 v high speed input voltage, single ended -0.3 vcc+0.5 v high speed input voltage, differential 2.5 v low speed output current -20 20 ma optical receiver input average power 1.5 dbm n ote: 1. the module supply voltages, vcct and vccr must not differ by more than 0.5 v or damage to the device may occur. table 4 . recommended o perating conditions recommended operating conditions specify parameters for which the electrical and optical characteristics hold un- less otherwise noted. optical and electrical charactristics are not defined for operation outside the recommended operating conditions, reliability is not implied and damage to the module may occur for such operation over an extended period of time. parameter symbol minimum maximum unit n otes case operating temperature t c 0 70 c note 1 module supply voltage vcct, vccr 3.135 3.465 v signal rate 10.311 10.313 gbd note 3 1000base-lx (1.25gbd typical) power supply noise tolerance 66 mvp-p note 2 including ripple tx input single ended dc v -0.3 4.0 v voltage tolerance (ref veet) rx output single ended voltage tolerance v -0.3 4.0 v n otes: 1. ambient operating tempera ture limits are based on the case operating temperature limits and are subject to the host system thermal design. see figure 6 for the module tc reference point. 2. the power supply filter (psf) and resulting power supply noise tolerance (psnt) are specified in the sff 8431 msa. the psnt value applies over the range from 10hz to 10mhz. 3. for 10gbase-lr
10 table 6. high speed signal electrical characteristics the following characteristics are defined over the recommended operating conditions unless otherwise noted. parameter symbol minimum typical maximum unit n otes tx input differential voltage, |(td +) - (td-)| v i 180 700 mv note 1 tx input ac common mode voltage tolerance 15 mv(rms) tx input differential s-parameter (100 ref.) sdd11 note 3 db 0.01-11.1 ghz tx input reflected differential to scd11 -10 db 0.01-11.1 ghz common mode conversion (25 ref.) rx output differential voltage, |(rd +) - (rd-)| vo 300 850 mv note 2 rx output termination mismatch @ 1mhz z m 5 % rx output ac common mode voltage 7.5 mv(rms) note 5 rx output output rise and fall time tr, tf 28 ps (20% to 80%) rx output total jitter tj 0.70 ulp-p note 6, 10gbd 0.332 uip-p 1.25gbd rx output 99% jitter dj 0.42 ulp-p rx output differential s-parameter (100 ref.) sdd22 note 4 db 0.01-11.1 ghz rx output common mode reflection scc22 -6 db 0.01-2.5 ghz coefficient (25 ref.) -3 db 2.5-11.1 ghz receiver output eye mask see figure 4a n otes: 1. internally ac coupled and terminated (100 ohm differential). 2. internally ac coupled but requires an external load termination (100 ohm differential). 3. reflection coefficient given by equation sdd11(db)=max(-12 + 2*sqrt(f ) -6.3+13log10(f/5.5)), with f in ghz. 4. differential output s-parameter given by equation sdd22(db)= max(-12 + 2*sqrt(f ) -6.3+13log10(f/5.5)), with f in ghz. 5. the rms value is measured by calculating the standard deviation of the histogram for one ui of the common mode signal. 6. tj conditions per sff-8431 table 5 . low speed signal electrical characteristics the following characteristics are defined over the recommended operating conditions unless otherwise noted. typical values are for tc = 40c. vcct and vccr = 3.3 v. parameter symbol minimum typical maximum unit n otes module supply current i cc 258 289 ma note 1 power dissipation p diss 850 1000 mw tx_fault, rx_los i oh - 50 + 37.5 a note 2 v ol - 0.3 0.4 v tx_disable v ih 2.0 vcct + 0.3 v note 3 v il -0.3 0.8 v n otes: 1. supply current includes both vcct and vccr connections. 2. measured with a 4.7 k load to vcchost. 3. tx_disable has an internal 4.7 k to 10 k pull-up to vcct
11 table 7. two- w ire interface electrical characteristics parameter symbol minimum maximum unit conditions host vcc range vcchtwi 3.135 3.465 v scl and sda v ol 0.0 0.40 v rp [1] pulled to vcchtwi, v oh vcchtwi - 0.5 vcchtwi + 0.3 v measured at host side of connector scl and sda v il -0.3 vcct*0.3 v v ih vcct*0.7 vcct + 0.5 v input current on the i l -10 10 a scl and sda contacts capacitance on scl c i [2] 14 pf and sda contacts total bus capacitance c b [3] 100 pf at 400 khz, 3.0 k rp, max for scl and for sda at 100 khz, 8.0 k rp, max 290 pf at 400 khz, 1.1 k rp, max at 100 khz, 2.75 k rp, max n otes: 1. rp is the pull up resistor. active bus termination may be used by the host in place of a pullup resistor. pull ups can be co nnected to various power supplies, however the host board design shall ensure that no module contact has voltage exceeding vcct or vccr by 0.5 v n or requires the module to sink more than 3.0 ma current. 2. c i is the capacitance looking into the module scl and sda contacts 3. c b is the total bus capacitance on the scl or sda bus. figure 4 a. 10 g bd receiver electrical o ptical eye mas k definition figure 4 b. 10 g bd transmitter o ptical eye mas k definition 15 0 0 -15 0 -4 2 5 0 0.3 5 1 . 0 0.6 5 abs o lu t e ampl it ude - m v no rmal i zed ti me ( u nit int er v al ) 4 2 5 1 .0 0.7 5 0.73 0. 5 0.2 8 0.2 5 0 - 0. 4 0 0 0.2 5 0. 4 0 0. 45 1 0. 55 0.60 0.7 5 no rmal i zed ampl it ude no rmal i zed ti me ( u nit int er v al ) 1 . 4 0
12 table 8 a. o ptical specifications the following characteristics are defined over the recommended operating conditions unless otherwise noted. parameter minimum typical maximum units n otes transmitter laser oma output power -5.2 dbm 1 laser mean output power -8.2 0.5 dbm 1 laser off power -30 dbm 1 extinction ratio 3.5 db 1 transmitter and dispersion penalty (tdp) 3.2 db 1 center wavelength 1260 1355 nm side mode suppression ratio - smsr 30 db rin 12 oma -128 db/hz 1 optical return loss tolerance 12 db 1 transmitter output eye mask 1, see figure 4b receiver stressed sensitivity (oma) -10.3 dbm 1, 2 receive sensitivity (oma) -12.6 dbm receive power (p ave ) overload 0.5 dbm 1 receive electrical 3db upper cutoff frequency 12.3 ghz reflectance -12 db 1 center wavelength 1260 1355 nm 1 rx_los (oma) de-assert -17 dbm 3 rx_los (oma) assert -30 dbm 3 rx_los (oma) hysteresis 0.5 db vertical eye closure penalty 2.2 db 2 stressed eye jitter 0.3 ui p-p 2 g eneral specification considerations ( n otes): 1. ieee 802.3ae clause 52 compliant. 2. vertical eye closure and stressed eye jitter are test conditions for stressed sensitivity (oma) measurements 3. loss of signal (los) detection responds only to oma and the indicator will respond unpredictably with the application of un modulated optical power.
13 table 8 b. 1.2 5g bd o ptical characteristics parameter symbol minimum typical maximum unit n otes transmitter output optical power (average) pout -9.5 -3 dbm optical extinction ratio er 9 db total jitter (tp1 to tp2 contribution) tj 227 ps 0.284 ui center wavelength 1260 1355 nm rms spectral width 4 nm laser off power -30 dbm rin (max) -120 db/hz receiver receiver sensitivity (average optical input power) -19 dbm stressed receiver sensitivity -14.4 dbm total jitter (tp3 to tp4 contributed 1.25gbd) tj 266 ps 0.332 ui average receive power (max) -3 dbm return loss (min) 12 db los de-assert pd -20 dbm los assert pa -30 dbm hysteresis pd-pa 0.5 db receive electrical 3db upper cutoff frequency 2.5 4 ghz wavelength 1260 1355 nm
14 table 9. control functions: low speed signals timing characteristics the following characteristics are defined over the recommended operating conditions unless otherwise noted. parameter symbol minimum maximum unit n otes tx_disable assert time t_off 100 s note 1 , fig. 5 tx_disable negate time t_on 2 ms note 2 , fig. 5 time to initialize, including reset of tx_fault t_init 300 ms note 3 , fig. 5 tx_fault assert time t_fault 1000 s note 4 , fig. 5 tx_disable to reset t_reset 10 s note 5 , fig. 5 rx_los assert time t_los_on 100 s note 6 , fig. 5 rx_los deassert time t_los_off 100 s note 7 , fig. 5 rate select time t_rate 40 ms n otes: 1. time from rising edge of tx_disable to when the optical output falls below 10% of nominal. a 10 ms interval between assertio ns of tx_disable is required. 2. time from falling edge of tx_disable to when the modulated optical output rises above 90% of nominal. 3. time from power on or falling edge of tx_disable to when the modulated optical output rises above 90% of nominal and the two -wire interface is available. 4. from power on or negation of tx_fault using tx_disable. 5. time tx_disable must be held high to reset the laser fault shutdown circuitry. 6. time from loss of optical signal to rx_los assertion. 7. time from valid optical signal to rx_los de-assertion. parameter symbol minimum maximum unit n otes tx_disable assert time t_off_twi 100 ms note 1 tx_disable negate time t_on_twi 100 ms note 2 tx_fault assert time t_fault_twi 100 ms note 3 rx_los assert time t_loss_on_twi 100 ms note 4 rx_los deassert time t_loss_off_twi 100 ms note 5 analog parameter data ready t_data 1000 ms note 6 two-wire interface ready t_serial 300 ms note 7 complete single or sequential write up to 4 byte t_write 40 ms note 8 complete sequential write of 5-8 byte t_write 80 ms note 8 two-wire interface clock rate f_serial_clock 400 khz note 8 time bus free before new t_buf 20 s note 9 transmission can start table 10. control functions: two- w ire interface timing characteristics the following characteristics are defined over the recommended operating conditions unless otherwise noted. n otes: 1. time from two-wire interface assertion of tx_disable (a2h, byte 110, bit 6) to when the optical output falls below 10% of no minal. measured from falling clock edge after stop bit of write transaction. 2. time from two-wire interface de-assertion of tx_disable (a2h, byte 110, bit 6) to when the modulated optical output rises ab ove 90% of nominal. 3. time from fault to two-wire interface tx_fault (a2h, byte 110, bit 2) asserted. 4. time for two-wire interface assertion of rx_los (a2h, byte 110, bit 1) from loss of optical signal. 5. time for two-wire interface de-assertion of rx_los (a2h, byte 110, bit 1) from presence of valid optical signal. 6. from power on to data ready bit asserted (a2h, byte 110, bit 0). data ready indicates analog monitoring circuitry is functio nal. 7. time from power on until module is ready for data transmission over the two-wire interface (reads or writes over a0h and a2h ). 8. operation of the two wire serial interface at rtes beyond 100khz requires the use of clock stretching techniques. 9. between stop and start. see sff 8431 section 4.3
15 table 11. transceiver digital diagnostic monitor (real time sense) characteristics the following characteristics are defined over the recommended operating conditions unless otherwise noted. parameter symbol min. units n otes transceiver internal temperature t int 3.0 c temperature is measured internal to the transceiver. valid from = -10c to 85c case temperature. transceiver internal supply v int 0.1 v supply voltage is measured internal to the transceiver voltage and can, with less accuracy, be correlated to voltage at the vcct contact. valid over 3.3 v 10%. transmitter laser dc bias current i int 10 % i int accuracy is better than 10% of the nominal value. transmitted average optical p t 3.0 db average power coupled into 9/125 m single-mode output power fiber. valid from151 w to 1120 w. received average optical input p r 3.0 db average power coupled from 9/125 m single-mode power fiber. valid from 25 w to 1120 w. figure 5 . transceiver timing diagrams (module installed and power applied except where noted) tx_fault v cc t, v cc r > 2.97 v t_init tx_disable transmitted signal t_init tx_fault v cc t, v cc r > 2.97 v tx_disable transmitted signal t-init: tx disable negated t-init: tx disable asserted tx_fault v cc t, v cc r > 2.97 v t_init tx_disable transmitted signal t_off tx_fault tx_disable transmitted signal t-init: tx disable negated, module hot plugged t-off & t-on: tx disable asserted then negated insertion t_on tx_fault occurance of fault t_fault tx_disable transmitted signal tx_fault occurance of fault tx_disable transmitted signal t-fault: tx fault occured t-reset: tx disable asserted then negated, tx signal recovered t_reset t_init* * sfp shall clear tx_fault in < t_init if the failure is transient tx_fault occurance of fault t_fault tx_disable transmitted signal optical signal los t-fault: tx disable asserted then negated, tx signal not recovered t-los-on & t-los-off t_loss_on t_init* t_reset * sfp shall clear tx_fault in < t_init if the failure is transient t_loss_off occurance of loss
16 table 12. eepr o m serial id memory contents C conventional sfp memory (address a0h) byte # decimal data hex n otes byte # decimal data hex n otes 0 03 sfp physical device 37 00 hex byte of vendor oui [1] 1 04 sfp function defined by serial id only 38 17 hex byte of vendor oui [1] 2 07 lc optical connector 39 6a hex byte of vendor oui [1] 3 20 10gbase-lr 40 41 a - vendor part number ascii character 4 00 41 46 f - vendor part number ascii character 5 00 42 43 c - vendor part number ascii character 6 02 1000base-lx 43 54 t - vendor part number ascii character 7 00 44 2d - - vendor part number ascii character 8 00 45 37 7 - vendor part number ascii character 9 00 46 30 0 - vendor part number ascii character 10 00 47 31 1 - vendor part number ascii character 11 06 64b/66b 48 53 s - vendor part number ascii character 12 67 10312.5 mbit/sec nominal bit rate (10.3125 gbit/s) 49 44 d - vendor part number ascii character 13 00 unspecified 50 44 d - vendor part number ascii character 14 0a 10gbase-lr 10km 51 5a z - vendor part number ascii character 15 64 10gbase-lr 10km 52 20 - vendor part number ascii character 16 00 53 20 - vendor part number ascii character 17 00 54 20 - vendor part number ascii character 18 00 55 20 - vendor part number ascii character 19 00 56 20 - vendor part number ascii character 20 41 a - vendor name ascii character 57 20 - vendor part number ascii character 21 56 v - vendor name ascii character 58 20 - vendor part number ascii character 22 41 a - vendor name ascii character 59 20 - vendor part number ascii character 23 47 g - vendor name ascii character 60 05 hex byte of laser wavelength [2] 24 4f o - vendor name ascii character 61 1e hex byte of laser wavelength [2] 25 20 - vendor name ascii character 62 00 26 20 - vendor name ascii character 63 checksum for bytes 0-62 [3] 27 20 - vendor name ascii character 64 00 receiver limiting output. 1 watt power class. 28 20 - vendor name ascii character 65 3a hardware sfp tx_disable, tx_fault, rx_los & rate_select 29 20 - vendor name ascii character 66 00 30 20 - vendor name ascii character 67 00 31 20 - vendor name ascii character 68-83 vendor serial number ascii characters [4] 32 20 - vendor name ascii character 84-91 vendor date code ascii characters [5] 33 20 - vendor name ascii character 92 68 digital diagnostics, internal cal, rx pwr avg 34 20 - vendor name ascii character 93 fa a/w, soft sfp tx_disable, tx_fault, rx_los, & rate_select 35 20 - vendor name ascii character 94 03 sff-8472 compliance to revision 10.2 36 00 95 checksum for bytes 64-94 [3] 96 - 255 00 n otes: 1. the ieee organizationally unique identifier (oui) assigned to avago technologies is 00-17-6a (3 bytes of hex).. 2. laser wavelength is represented in 16 unsigned bits. 3. addresses 63 and 95 are checksums calculated (per sff-8472) and stored prior to product shipment. 4. addresses 68-83 specify the afct-701sddz ascii serial number and will vary on a per unit basis. 5. addresses 84-91 specify the afct-701sddz ascii date code and will vary on a per date code basis.
17 table 13. eepr o m serial id memory contents C enhanced feature set memory (address a2h) byte # byte # byte # decimal n otes decimal n otes decimal n otes 0 temp h alarm msb [1] 26 tx pwr l alarm msb [4] 104 real time rx pwr msb [5] 1 temp h alarm lsb [1] 27 tx pwr l alarm lsb [4] 105 real time rx pwr lsb [5] 2 temp l alarm msb [1] 28 tx pwr h warning msb [4] 106 reserved 3 temp l alarm lsb [1] 29 tx pwr h warning lsb [4] 107 reserved 4 temp h warning msb [1] 30 tx pwr l warning msb [4] 108 reserved 5 temp h warning lsb [1] 31 tx pwr l warning lsb [4] 109 reserved 6 temp l warning msb [1] 32 rx pwr h alarm msb [5] 110 status/control - see table 14 7 temp l warning lsb [1] 33 rx pwr h alarm lsb [5] 111 reserved 8 vcc h alarm msb [2] 34 rx pwr l alarm msb [5] 112 flag bits - see table 15 9 vcc h alarm lsb [2] 35 rx pwr l alarm lsb [5] 113 flag bits - see table 15 10 vcc l alarm msb [2] 36 rx pwr h warning msb [5] 114 reserved 11 vcc l alarm lsb [2] 37 rx pwr h warning lsb [5] 115 reserved 12 vcc h warning msb [2] 38 rx pwr l warning msb [5] 116 flag bits - see table 15 13 vcc h warning lsb [2] 39 rx pwr l warning lsb [5] 117 flag bits - see table 15 14 vcc l warning msb [2] 40-55 reserved 118 extended control/status byte. see table 16 15 vcc l warning lsb [2] 56-94 external calibration constants [6] 119-127 reserved 16 tx bias h alarm msb [3] 95 checksum for bytes 0-94 [7] 128-247 customer writeable 17 tx bias h alarm lsb [3] 96 real time temperature msb [1] 248-255 vendor specific 18 tx bias l alarm msb [3] 97 real time temperature lsb [1] 19 tx bias l alarm lsb [3] 98 real time vcc msb [2] 20 tx bias h warning msb [3] 99 real time vcc ls [2] 21 tx bias h warning lsb [3] 100 real time tx bias msb [3] 22 tx bias l warning msb [3] 101 real time tx bias lsb [3] 23 tx bias l warning lsb [3] 102 real time tx power msb [4] 24 tx pwr h alarm msb [4] 103 real time tx power lsb [4] 25 tx pwr h alarm lsb [4] n otes: 1. temperature (temp) is decoded as a 16 bit sig ned twos compliment integer in increments of 1/256c. 2. supply voltage (vcc) is decoded as a 16 bit unsigned integer in increments of 100 v. 3. laser bias current (tx bias) is decoded as a 16 bit unsigned integer in increments of 2 a. 4. transmitted average optical power (tx pwr) is decoded as a 16 bit unsigned integer in increments of 0.1 w. 5. received average optical power (rx pwr) is decoded as a 16 bit unsigned integer in increments of 0.1 w. 6. bytes 56-94 are not intended for use with afct-701sddz, but have been set to default values per sff-8472. 7. byte 95 is a checksum calculated (per sff-8472) and stored prior to product shipment.
18 table 1 4 . eepr o m serial id memory contents C soft commands (address a2h, byte 110) status/ bit # control n ame description n otes 7 tx_ disable state digital state of sfp tx_ disable input (1 = tx_disable asserted) note 1 6 soft tx_ disable read/write bit for changing digital state of tx_disable function note 1, 2 5 reserved 4 reserved 3 soft rs0 select read/write bit that allows software rx rate control. writing 1 selects full speed rx operation. power on default is logic zero/low. this bit is ord with the hardware rs0 pin value (see appendix). 2 tx_fault state digital state of the sfp tx_fault output (1 = tx_fault asserted) note 1 1 rx_los state digital state of the sfp rx_los output (1 = rx_los asserted) note 1 0 data ready (bar) indicates transceiver is powered and real time sense data is ready. (0 = ready) n otes: 1. the response time for soft commands of the afct-701sddz is 100 msec as specified by sff-8472. 2. bit 6 is logic ord with the sfp tx_disable input on contact 3; either asserted will disable the sfp+ transmitter. table 1 5 . eepr o m serial id memory contents C alarms and w arnings (address a2h, bytes 112, 113, 116, 117) byte bit flag bit n ame description 112 7 temp high alarm set when transceiver internal temperature exceeds high alarm threshold 6 temp low alarm set when transceiver internal temperature exceeds low alarm threshold 5 vcc high alarm set when transceiver internal supply voltage exceeds high alarm threshold 4 vcc low alarm set when transceiver internal supply voltage exceeds low alarm threshold 3 tx bias high alarm set when transceiver laser bias current exceeds high alarm threshold 2 tx bias low alarm set when transceiver laser bias current exceeds low alarm threshold 1 tx power high alarm set when transmitted average optical power exceeds high alarm threshold 0 tx power low alarm set when transmitted average optical power exceeds low alarm threshold 113 7 rx power high alarm set when received average optical power exceeds high alarm threshold 6 rx power low alarm set when received average optical power exceeds low alarm threshold 0-5 reserved 116 7 temp high warning set when transceiver internal temperature exceeds high warning threshold 6 temp low warning set when transceiver internal temperature exceeds low warning threshold 5 vcc high warning set when transceiver internal supply voltage exceeds high warning threshold 4 vcc low warning set when transceiver internal supply voltage exceeds low warning threshold 3 tx bias high warning set when transceiver laser bias current exceeds high warning threshold 2 tx bias low warning set when transceiver laser bias current exceeds low warning threshold 1 tx power high warning set when transmitted average optical power exceeds high warning threshold 0 tx power low warning set when transmitted average optical power exceeds low warning threshold 117 7 rx power high warning set when received average optical power exceeds high warning threshold 6 rx power low warning set when received average optical power exceeds low warning threshold 0-5 reserved
19 figure 6. module drawing tcase reference point latch color blue: 10gbaselr 0.82 uncompressed 0.69 uncompressed 6.25 tx rx 14.9 uncompressed 12.27 8.5 0.1 13.7 9.7 13.6 47.5 13.4 0.1 table 16. eepr o m serial id memory contents - extended control/status (address a2h, byte 11 8 ) bit # status/ control n ame description n otes 7 reserved 6 reserved 5 reserved 4 reserved 3 soft rs1 select read/write bit that allows software tx rate control. writing '1' selects full speed tx operation. power on default is logic zero/low. this bit is or'd with the hard- ware rs1 pin value (see appendix). 1 2 reserved 1 class2 operation state value=0. power class2 operation is not active. 0 power class select has no effect. notes: 1. the response time for soft commands of the afct-701sddz is 100ms as specified by sff-8472.
for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2011 avago technologies. all rights reserved. av02-1965en - january 18, 2011 appendix: rate select control rx and tx rates can be independently controlled by either hardware input pins or via register writes. module electri- cal input pins 7 and 9 are used to select rx and tx rate respectively. status of each logic level is reflected to register byte 110 bit 4 and 5 on address a2h as shown in the diagram below. rx and tx rates can also be controlled by register writes to byte 110 bit 3 and 118 bit 3. power on default of these bits are logic low. hardware and software control inputs are ord to allow flexible control. rs1 tx rate select control flow rs0 control input rx o peration hardware software 0 0 1.25g 0 1 10g 1 0 10g 1 1 10g rs1 control input tx o peration hardware software 0 0 1.25g 0 1 10g 1 0 10g 1 1 10g rs0 ( p i n7 ) voltage "1" ... v> 2.0 " 0 " ... v< 0.8 a2 h, byte 11 0 b it 3 or a2 h, byte 11 0 b it 4 rx r ate c ontrol s oftware input hardware input rs 1 ( p i n9 ) voltage "1" ... v> 2.0 " 0 " ... v< 0.8 a2 h, byte 11 8 b it 3 or a2 h, byte 11 0 b it 5 t x r ate c ontrol s oftware input hardware input rs0 rx rate select control flow

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